1. Field of the Invention
Aspects of the present invention relate generally to integrated devices and more particularly to organic laminate stack ups.
2. Description of the Related Art
Today typical printed circuit board assembly processes can be categorized into two modes of assembly: a) through hole assembly and b) surface mount assembly (SMA). While both are used widely, SMA is the generally preferred assembly method when an objective is to reduce size and increase performance. Using SMA processes, one can readily assemble both active and passive components, which may be generally referred to as surface mount devices (SMD). Surface mount active and passive components typically have been placed on the outermost layer of a printed circuit board. The surface mounted components can be either on the top side, bottom side, or both on the top and bottom of the printed circuit board. The component attachment is typically accomplished by printing solder paste on the surface of the printed circuit board using a stencil that is typically held down by a vacuum source mated against the printed circuit board. The solder paste is screened through openings in the stencil onto pads of the printed circuit board. After application of the solder paste the surface mount components are then placed onto the soldered pasted sites using a pick and place machine. Pick and place machines, which are almost always automated, typically use a vision system to ensure appropriate alignment and accurate placement of surface mount components. Upon placement of the components, the entire printed circuit board assembly with the placed components is now reflowed in an appropriate oven to achieve a reliable interconnect between the printed circuit board and the components.
The above-described process, although widely used to reduce the overall size of the printed circuit board assembly, still has many challenges. These challenges include microminiaturization, reliability, and performance. As system speeds and frequencies increase, it becomes imperative to minimize parasitics. For digital based systems, this equates to delay and for RF (radio frequency) based systems, this translates into reduction in gain. In any case, system performance suffers.
Thus, it may be desirable to reduce interconnect lengths, improve reliability, reduce system size, reduce costs, and improve flexibility in design.